Multi-standard lighting control interface circuit

ABSTRACT

Lighting control interface techniques and corresponding circuitry are provided. The techniques include receiving a first signal potentially representative of a first lighting control signal, and receiving a second signal potentially representative of a second lighting control signal, and determining if either of the first and second signals complies with a first or second lighting control protocol. The lighting control signal may be applied to the same interface connector (regardless of the protocol), thereby eliminating the need for separate dedicated interface connectors. In some cases, the techniques further include determining that a dummy control signal is manifesting in the first and/or second signals, thereby indicating that no lighting control signal is being applied. Depending on the resulting determination, the techniques may include, for example, setting output lighting power according to a pre-established value, or according to the first or second lighting control protocol.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of, and claims the benefit ofpriority of, U.S. patent application No. 15/646,071, filed Jul. 10,2017, which is a continuation of, and claims the benefit of priority of,U.S. patent application No. 13/967,385, now U.S. Pat. No. 9,706,621,filed Aug. 15, 2013, the entire contents of both of which are herebyincorporated by reference.

TECHNICAL FIELD

The present invention relates to lighting, and more specifically, tolighting control interface circuits.

BACKGROUND

There are a number of lighting control standards currently available foruse by lighting products. For example, DALI (Digital AddressableLighting Interface) and 0 to 10V are two commonly used lighting controlstandards. While a DALI compliant control signal is digital, a 0-10Vcompliant control signal is analog. A DALI interface is bidirectionaland is specified in IEC standard 62386. The high level of aDALI-compliant control signal is 9.5 to 22.5V (typical 16 V), and thelow level is −6.5 to 6.5V (typical 0V). A lighting control device, suchas a ballast or a solid state light source driver, as a DALI slavecomponent, may consume only 2.0 mA or less from the DALI interface. ADALI interface works with a non-reversed or a reversed DALI signalconnection. In contrast, a 0-10V control signal is a DC voltage thatvaries between 0 and 10 VDC to produce a varying light intensity level.There are two existing 0-10V standards, one of which is for currentsourcing controls and is supported by the standard ESTA E1.3,Entertainment Technology-Lighting Control System-0-10V Analog ControlProtocol, Draft 9 June 1997. The other available 0-10V standard is forcurrent sink controls, which is specified in IEC standard 60929 Annex E.

SUMMARY

There are a number of non-trivial issues associated with complying withthe various available lighting control protocols. For instance, in somecases where the lighting control interface is to support multiplestandards such as DALI, 0-10V (current sink or source), and/or othersuch lighting protocols, a separate interface is required for each suchprotocol, thereby requiring a distinct or otherwise dedicated interfaceconnector for each protocol. Such connectors and the associatedfabrication costs are relatively expensive and also take up asignificant amount of physical space per connector. In addition, whilesome requirements apply to multiple standards, other requirements areunique to a given standard and do not apply to other standards. As such,an interface circuit that works for one standard would not necessarilybe appropriate for another standard.

Thus, embodiments provide a lighting control interface circuit thatreceives control signals from multiple standards at a common connector(e.g., the same two terminals or contact pads of a single connector).The interface circuit provides a first protocol output and a secondprotocol output. These outputs may be digital, analog or a combination.For instance, the first protocol output could be an analog output for0-10V compliant signals and the second protocol output could be adigital output for DALI compliant signals. A microcontroller unit (MCU)or other suitable processor receives the various outputs of theinterface circuit and recognizes the existence of the respectiveprotocols (e.g., DALI digital signal, 0-10V analog signal, etc), andthen processes the control signal accordingly. The MCU also detects ifno control signal is connected to the interface circuit. In someembodiments, the interface circuit includes a common connectoroperatively coupled to a first protocol signal processing section whichis in turn operatively coupled to a second protocol signal processingsection. In such embodiments, the first protocol signal processingsection effectively passes through a signal having a second protocol.Thus, if a second protocol signal is applied to the interface, theMCU/processor will assess how that signal manifests at the output of thefirst protocol signal processing section as well as at the output of thesecond protocol signal processing section, and is configured todetermine that the output of the second protocol signal processingsection is the most correct choice and will power a ballast/drivercircuit connected thereto in accordance with that output/protocol, andwill ignore the output of the first protocol signal processing section.In a similar fashion, if a first protocol signal is applied to theinterface, the MCU/processor will assess how that signal manifests atthe output of the first protocol signal processing section as well as atthe output of the second protocol signal processing section, and isconfigured to determine that the output of the first protocol signalprocessing section is the most correct choice and that the output of thesecond protocol signal processing section should be ignored.

In some embodiments, the interface circuit is configured to operate withboth DALI and 0-10V control signals using the same two connectors. Insome such embodiments, the 0-10V protocol section is implemented at thefront end of the interface circuit and is configured with a differentialamplifier and a linear opto-isolation amplifier to provide the analog0-10V output and for galvanic isolation. The DALI protocol section isimplemented at the output of 0-10V protocol section and is configuredwith a translation sub-circuit to provide the digital DALI output. TheMCU or other processor connected to the respective outputs of the 0-10Vand DALI protocol sections may recognize the existence of the DALIdigital control signal or the 0-10V analog control signal. Note that anychanges made to a DALI signal caused by processing through the 0-10Vprotocol section may be recognized and corrected or otherwisecompensated for by the processor. The processor may then process thelighting control signal accordingly.

In some embodiments, and with respect to recognizing that no controlsignal is connected, the interface circuit may include an on-boardsignal generator sub-circuit configured to apply a signal to the inputterminals. In such embodiments, if no control signal is connected to thecommon connector terminals, the output of the interface circuit willresemble or otherwise indicate the signal produced by the signalgenerator sub-circuit. On the other hand, if a lighting control signalcomplying with a given protocol is connected to the common connectorterminals, the signal produced by the signal generator sub-circuit iseffectively suppressed and the output of the interface circuit willresemble or otherwise indicate the protocol of the applied lightingcontrol signal. In one such embodiment, for example, a 0-10V lightingcontroller that has relatively low output impedance compared to theoutput impedance of the signal generator sub-circuit (in someembodiments) is connected to the interface. As such, the signal outputby the signal generator sub-circuit is effectively suppressed by theapplied 0-10V control signal. A similar suppression of the signalproduced by the signal generator sub-circuit occurs if a DALI lightingcontroller is present at the input. An MCU or other processor may beprogrammed or otherwise configured to identify a given control signaltype by parameters indicative of that protocol or the signal output bythe signal generator sub-circuit by parameters indicative of thatsignal, and drive the ballast/light circuit accordingly. Any one or morestandards-based processing sections may be used in conjunction with sucha signal generator sub-circuit, wherein the signal generator sub-circuitallows the condition of no control signal at the interface input to berecognized.

The interface circuit may be configured with other features orfunctionality. For instance, the interface circuit may also beconfigured to recognize the conditions of input signal polarity reverseand/or signal level. The interface circuit may also be configured towithstand a wide voltage range at its input. In some embodiments, theinterface circuit may withstand voltage between −20 VDC and +20 VDC. Thecircuit may also be configured to withstand high AC voltage at itsinput, such as 120 VAC. In some embodiments, the interface circuit isconfigured with an isolated DC/DC converter and opto-isolationamplifier, so as to provide isolation of control signals from AC mains(line and neutral). Numerous other features and functionality will beapparent in light of this disclosure and may depend on various factorssuch as, for example but not limited to, applicable lightingstandards/protocols, desired lighting performance, and/or existinglighting infrastructure.

In an embodiment, there is provided a lighting control interfacecircuit. The lighting control interface circuit includes: an interfaceconnector configured to receive a lighting control signal; a controlsignal processing circuit operatively coupled to the interface connectorand having a first processing section that provides a first outputsignal at a first output; and a processor configured to receive thefirst output signal via the first output and to determine if a lightingcontrol signal is being applied at the interface connector based on thefirst output signal.

In a related embodiment, the processor may be further configured todetermine if a lighting control signal applied at the interfaceconnector complies with one of a first lighting control protocol and asecond lighting control protocol. In another related embodiment, thelighting control interface circuit may further include a signalgenerator circuit operatively coupled to the interface connector andconfigured to provide a dummy control signal at an output of the controlsignal processing circuit as an indicator to the processor that nolighting control signal is currently applied to the interface connector.In a further related embodiment, the processor may be further configuredto detect the dummy control signal at an output of the control signalprocessing circuit. In another further related embodiment, a lightingcontrol signal applied to the interface connector may override the dummycontrol signal. In yet another further related embodiment, the processormay be configured to detect the dummy control signal at the first outputwhen no lighting control signal is applied to the interface connector.

In still another related embodiment, the control signal processingcircuit may further include a second processing section operativelycoupled to the first output and configured to provide a second outputsignal at a second output. In a further related embodiment, theprocessor may be further configured to receive the second output signaland to determine if the second output signal complies with a lightingcontrol protocol in a plurality of lighting control protocols.

In yet another related embodiment, the first processing section mayinclude an isolation amplifier, and the lighting control interfacecircuit may further include an isolated power supply configured toprovide power to one side of the isolation amplifier. In still anotherrelated embodiment, the lighting control interface circuit may furtherinclude a transmitter communicatively coupled between the processor andthe interface connector, and configured to allow the processor tocommunicate with a lighting controller connected to the interfaceconnector.

In another embodiment, there is provided a lighting control interfacecircuit. The lighting control interface circuit includes: an interfaceconnector configured to receive a lighting control signal that iscompliant with a lighting control protocol in a plurality of lightingcontrol protocols; a control signal processing circuit operativelycoupled to the interface connector, wherein the control signalprocessing circuit comprises an isolation amplifier configured toprovide a first output signal at a first output, and a signal translatoroperatively coupled to the first output and configured to provide asecond output signal at a second output; and a processor configured toreceive the first and second output signals and to determine if alighting control signal applied at the interface connector complies witha lighting control protocol in the plurality of lighting controlprotocols.

In a related embodiment, the lighting control interface circuit mayfurther include: a signal generator circuit operatively coupled to theinterface connector and configured to provide a dummy control signal atan output of the control signal processing circuit as an indicator tothe processor that no lighting control signal is currently applied tothe interface connector. In a further related embodiment, the processormay be further configured to detect the dummy control signal at anoutput of the control signal processing circuit. In another furtherrelated embodiment, the processor may be configured to detect the dummycontrol signal at the first output when no lighting control signal isapplied to the interface connector.

In yet another related embodiment, the lighting control interfacecircuit may further include at least one of: an isolated power supplyconfigured to provide power to one side of the isolation amplifier; anda transmitter communicatively coupled between the processor and theinterface connector configured to allow the processor to communicatewith a lighting controller connected to the interface connector.

In another embodiment, there is provided a method of interfacinglighting controls. The method includes: receiving a first signalpotentially representative of a first lighting control signal; receivinga second signal potentially representative of a second lighting controlsignal; and determining if either of the first and second signalscomplies with a first lighting control protocol or a second lightingcontrol protocol.

In a related embodiment, the method may further include: determiningthat a dummy control signal is manifesting in at least one of the firstand second signals, thereby indicating that no lighting control signalis being applied. In a further related embodiment, in response todetermining that a dummy control signal is manifesting in at least oneof the first and second signals, the method may further include settingoutput lighting power according to a pre-established value.

In another related embodiment, in response to determining the firstsignal complies with a first lighting control protocol, the method mayfurther include setting output lighting power according to the firstlighting control protocol. In yet another related embodiment, inresponse to determining the second signal complies with a secondlighting control protocol, the method may further include setting outputlighting power according to the second lighting control protocol.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages disclosedherein will be apparent from the following description of particularembodiments disclosed herein, as illustrated in the accompanyingdrawings in which like reference characters refer to the same partsthroughout the different views. The drawings are not necessarily toscale, emphasis instead being placed upon illustrating the principlesdisclosed herein.

FIGS. 1A and 1B each illustrate a block diagram of a lighting controlinterface circuit according to embodiments disclosed herein.

FIG. 2 illustrates an example configuration of an isolated power supplyof the lighting control interface circuits of FIGS. 1A and 1B accordingto embodiments disclosed herein.

FIG. 3 illustrates an example configuration of an amplifier and anisolation amplifier of the lighting control interface circuits of FIGS.1A and 1B according to embodiments disclosed herein.

FIG. 4 illustrates an example configuration of a buffer and a signalgenerator of the lighting control interface circuits of FIGS. 1A and 1Baccording to embodiments disclosed herein.

FIG. 5 illustrates an example configuration of a signal translator ofthe lighting control interface circuits shown in FIGS. 1A and 1Baccording to embodiments disclosed herein.

FIG. 6 illustrates a transmitter of the lighting control interfacecircuits of FIGS. 1A and 1B according to embodiments disclosed herein.

FIG. 7 is a flowchart of methods carried out by one of the lightingcontrol interface circuits of FIGS. 1A and 1B according to embodimentsdisclosed herein.

DETAILED DESCRIPTION

FIG. 1A illustrates a block diagram of a lighting control interfacecircuit 100 (also referred to throughout as an interface circuit 100),which includes an interface connector 110, a buffer 112, an amplifier114, a signal generator 118, an isolation amplifier 120, an isolatedpower supply 122, a signal translator 124, and an MCU 126. The lightingcontrol interface circuit 100, in some embodiments, is, after theinterface connector 110, divided into a first protocol section (alsoreferred to as a front end and/or front end section) and a secondprotocol section. The first protocol section includes the amplifier 114and the isolation amplifier 120. The second protocol section includesthe signal translator 124. In some embodiments, one section or the otherincludes one or more of the remaining components (i.e., the buffer 112,the signal generator 118, the isolated power supply 122, the transmitter116, and/or the MCU 126). In some embodiments, one or more of thesecomponents may be spread across both sections, or in their own section.The interface circuit 100 is able to receive a control signal (such asbut not limited to at least one of the control signals 102 a, 102 bshown in FIG. 1A) from a lighting controller 104. The interface circuit100 determines which one of multiple lighting control protocols appliesto the received control signal 102 a, 102 b. Note that regardless of theprotocol being used to transmit the control signal from the lightingcontroller 104 to the interface circuit 100, the control signal isapplied to the same interface connector 110, which in FIG. 1A includestwo terminals A and B. Though FIG. 1A shows the interface circuit 100 asworking with two protocols, any number of protocols may be, and in someembodiments are, used, so long as the corresponding protocol of acontrol signal applied at the common interface connector 110 is able tobe identified. The lighting control interface circuit 100 is also ableto detect a no control signal condition at the common interfaceconnector 110.

The isolated power supply 122 provides power to the various sub-circuitsand/or components of the interface circuit 100. The amplifier 114 isoperatively connected to the two terminals A and B of the interfaceconnector 110. An output of the amplifier 114 is provided to anisolation amplifier 120, which in turn drives a signal translator 124.An output signal associated with a first lighting protocol, protocol #1in FIG. 1A, is taken at the output of the isolation amplifier 120, andan output signal associated with a second lighting protocol, protocol #2in FIG. 1A, is taken at the output of the signal translator 124. An MCU126 receives both of these outputs, evaluates the received signals, andgenerates an appropriate drive signal 128. The drive signal 128 is thenapplied to a ballast/driver 150, which provides appropriate power to alighting circuit connected thereto (not shown in FIG. 1A). Theballast/driver 150 is any type of ballast and/or driver circuit known inthe art. The interface circuit 100 also includes the signal generator118 and the buffer 112 for providing a dummy control signal to one orboth of the two terminals A and B, thereby allowing for a no controlsignal situation to be detected. The interface circuit 100 also includesan optional transmitter 116 for providing communications from the MCU126 back to the interface connector 110, and specifically back to one orboth of the two terminals A and B, thereby allowing for bi-directionalcommunication between the interface connector 110 and the MCU 126, whichis used and/or required by some lighting standards.

FIG. 1B shows another embodiment of a lighting control interface circuit100 a (also referred to throughout as an interface circuit 100 a),having some similar components to lighting control interface circuit 100shown in FIG. 1A. In FIG. 1B, the lighting control interface circuit 100a is integrated directly into a ballast/driver 150 a and receivessignals from a lighting controller 104 a, which in some embodiments isnot integrated with the ballast/driver 150 a, and in some embodimentsis. Other such integration schemes will be apparent in light of thisdisclosure. Components of the interface circuit 100/the interfacecircuit 100 a will now be discussed in turn. For ease of description,these components will be discussed in terms of a first lightingprotocol, i.e., protocol #1 in FIGS. 1A and 1B, being the 0-10V standardand a second lighting protocol, i.e. protocol #2 in FIGS. 1A and 1B,being the DALI standard. In such embodiments, the lighting controller104/the lighting controller 104 a may be, for example but not limitedto, a 0-10V dimmer, a DALI master controller, both, or other similarcomponents. Of course, embodiments are not so limited and thus may anddo use different lighting control protocols and/or lightingcontroller(s). Similarly, the interface connector 110 may be, and insome embodiments is, any standard or custom interface connector suitablefor the protocols to be supported, and may, and in some embodimentsdoes, include any number of terminals and/or other contacts needed tocommunicate the signal(s) of a given standard/protocol. As will beappreciated in light of this disclosure, and in some embodiments, acontrol signal compliant with a given one of various standards supportedby the interface circuit is able to be applied to the same interfaceconnector 110 as control signals compliant with others of the variousstandards, thereby eliminating the need for multiple interfaceconnectors. Thus, while the interface connector 110 shown in FIGS. 1Aand 1B includes two terminals A and B, other embodiments may and doinclude an interface connector having any number of terminals, such asbut not limited to a single terminal for +V with a connector plug casingfor −V, or three terminals that allow for +V, −V, and a dedicatedcommunication channel, respectively, and so on. Further, the interfaceconnector 110 may and does take any number of form factors and thus mayand does include, for example but not limited to, a plug/receptaclearrangement and/or wires directly soldered to corresponding conductorson a substrate, such as but not limited to a printed wiring board (PWB).The corresponding conductors to which the wires are soldered may be, forinstance, conductive pads or vias, or conductive runs or posts. In someembodiments, the interface connector is configured to wirelessly receivelighting control signals, in which embodiments the interface connectorincludes appropriate transmission and reception components, such as butnot limited to an antenna and receiver, transceiver, and the like,including combinations thereof, configured to receive lighting controlsignals of multiple protocols (e.g., rather than using a single physicalinterface connector to receive multiple protocols, a single wirelessinterface connector may be used). Thus, an interface connector is anywired or wireless input port for coupling a control signal into theinterface circuit, wherein the input port is singular in nature and mayreceive multiple control signal types thereby eliminating or otherwisereducing the need for a dedicated input port for each signal type.

In operation, the isolated power supply 122 receives external power(e.g., 120VAC @60 Hz, or 380VDC, or any other AC or DC voltage source),and generates any supply voltages needed to operate the interfacecircuit 100/100 a. In some embodiments, at least one of the generatedvoltages is isolated from the external power. The isolated power supply122 may be configured in any number of ways. In some embodiments, theisolated power supply 122 is configured as shown in FIG. 2. In FIG. 2,the isolated power supply 122 includes a converter U1 a for convertingthe external power to a first internal supply +V_(DD), −V_(DD), and anisolated DC-DC converter U1 b for converting the first internal supplyto a second internal supply +V_(Iso), −V_(Iso) that is isolated from thesource of the external power. The first internal supply +V_(DD), −V_(DD)may be, and in some embodiments is, also converted to a third internalsupply +V_(DD2), −V_(DD2), which may or may not be isolated.Alternatively, in some embodiments where only the first internal supply+V_(DD), −V_(DD) is needed, no third internal supply need be generated.As shown in FIG. 2, the first internal supply +V_(DD), −V_(DD) and thesecond internal supply +V_(Iso), −V_(Iso) are bipolar, but in otherembodiments, either or both may be unipolar. Due to the isolationamplifier 120, at least two supplies are provisioned: one for the inputside of the isolation amplifier 120 and related components, and one forthe output side of the isolation amplifier 120 and related components.In some embodiments, each of the amplifier 114, an input side of theisolation amplifier 120, the buffer 112, the signal generator 118, andan output side of the transmitter 116 are powered by an isolated powersource, such as but not limited to the second internal supply +V_(Iso),−V_(Iso) of the isolated power supply 122, and corresponding ground,such as but not limited to GND_(Iso) of the isolated power supply 122.At the same time, an output side of the isolation amplifier 120, thesignal translator 124, an input side of the transmitter 116, and the MCU126 are powered by another power source, such as but not limited to thefirst internal power supply +V_(DD), −V_(DD) or the third internal powersupply +V_(DD2), −V_(DD2) of the isolated power supply 122, andcorresponding ground. Within the isolated power supply 122, a number offilter capacitors C1, C2, C3, C4, C5 are used to mitigate any noise,ripple, etc from the provisioned internal power supply. In FIG. 2, thefilter capacitor C1 is connected between positive and negative outputs+VDC, −VDC of the converter U1 a, which generates the first internalpower supply +V_(DD), −V_(DD). The positive and negative outputs +VDC,−VDC of the converter U1 a are connected to positive and negative inputs+V_(IN), −V_(IN) of the isolated DC-DC converter U1 b, and to positiveand negative inputs +V_(IN), −V_(IN) of the voltage regulator U1 c. Theisolated DC-DC converter U1 b has three outputs, a positive output+V_(O), a negative output −V_(O), and a ground output GND. The secondinternal power supply +V_(Iso), −V_(Iso) and an isolated groundGND_(Iso) are generated by these outputs. The filter capacitor C2 isconnected between the positive output +V_(O) and the ground output GND.The filter capacitor C3 is connected between the negative output -Vo andthe ground output GND. The voltage regulator U1 c has three outputs, apositive output +V_(O), a negative output −V_(O), and a ground outputGND connected to ground. The third internal power supply +V_(DD2),−V_(DD2) and a ground are generated by these outputs. The filtercapacitor C4 is connected between the positive output +V_(O) and ground.The filter capacitor C5 is connected between the negative output −V_(O)and ground.

Returning to FIGS. 1A and 1B, the amplifier 114 receives the controlsignal 102 a, 102 b from one or both of the two terminals A and B of theinterface connector 110 and conditions the received control signal todrive the isolation amplifier 120. In some embodiments, the amplifier114 is implemented with a differential amplifier configuration using anysuitable op-amp or other similar component(s). The isolation amplifier120 effectively isolates the control signal(s) 102 a, 102 b input fromthe lighting controller 104/104 a from other signals, such that anyshort-circuit or other such adverse signal conditions in an input stageof the interface circuit 100/100 a will not be able to manifest at anoutput of the interface circuit 100/100 a. The isolation amplifier 120is implemented using, for example but not limited to, atransformer-based isolation barrier or an optical-based isolationbarrier, although any suitable isolation techniques may be used. In someembodiments, each of the amplifier 114 and the isolation amplifier 120is implemented with bipolar amplifiers, so that the input amplitude andpolarity information are presented at the output of the isolationamplifier 120.

In some embodiments, the amplifier 114 and the isolation amplifier 120are configured as shown in FIG. 3. FIG. 3 shows the amplifier 114implemented with a differential amplifier configuration that includes anop-amp U2, including an inverting input, a non-inverting input, andoutput, and two power terminals, along with resistors R1, R2, and R3,diodes D1 and D2, and Zener diodes Z1 and Z2. The Zener diodes Z1 and Z2are connected in series between the two terminal A and B. The isolatedground GND_(Iso) of the isolated power supply 122 is connected inbetween the Zener diodes Z1 and Z2. The diodes D1 and D2 are connectedin parallel across the inverting input and the non-inverting input ofthe op-amp U2. The resistor R1 is connected in series between terminal Aand the inverting input of the op-amp U2. The resistor R2 is connectedin series between terminal B and the non-inverting input of the op-ampU2. The second internal power supply +V_(Iso), −V_(Iso) generated by theisolated power supply 122 is connected to the two power terminals of theop-amp U2. The resistor R3 is connected across the output of the op-ampU2 and the inverting input of the op-amp U2. The isolation amplifier 120is implemented with an opto-isolation amplifier U3, along with resistorsR4 and R5, and capacitors C6, C7, C8, and C9. The opto-isolationamplifier U3 includes at least five terminals. A first terminal −V_(IN)and a first ground terminal GND₁ are each connected to the isolatedground GND_(Iso) of the isolated power supply 122. The capacitor C7 isconnected between the first terminal −V_(IN) and the positive portion+V_(Iso) of the second internal supply of the isolated power supply 122.The capacitor C6 is connected between a second terminal +V_(IN) and thefirst ground terminal GND₁. The resistor R4 is connected between thecapacitor C6 and the output of the op-amp U2 of the amplifier 114. Asecond ground terminal GND₂ is connected to ground. The capacitor C8 isconnected between the second ground terminal GND₂ and the positiveportion +V_(DD2) of the third internal supply of the isolated powersupply 122. The resistor R5 is connected to an output terminal +V_(O)and to the capacitor C9. The capacitor C9 is also connected to ground.An output voltage Vout, representing the first protocol protocol #1 istaken from a point between the resistor R5 and the capacitor C9.

In operation, the op-amp U2 of the amplifier 114 receives a controlsignal (e.g., 0-10V or DALI control signal) and conditions the signal todrive the opto-isolation amplifier U3 of the isolation amplifier 120.The configuration of the op-amp U2 and the opto-isolation amplifier U3means that the input amplitude and polarity information of the appliedcontrol signal will be presented at the output of the opto-isolationamplifier U3, i.e., at Vout. In some embodiments, the op-amp U2 is aTS912 op-amp by STMicroelectronics, and the otpo-isolation amplifier U3is a HCPL7510 iso-opto amplifier by Avago Technologies. In someembodiments, the resistors R1, R2, R3, and R4, and the capacitors C6,C7, C8, and C9 have the following values: R1 and R2=100KΩ, R3=2KΩ,R4=200Ω, and R5=1KΩ; C6=180pF, C7 and C8=100nF, and C9=10nF. Of course,numerous other suitable component manufacturers and component types andcomponent values may be, and in some embodiments are, used to implementthe amplifier and the isolation amplifier, and any specific examplesprovided here merely illustrate one possible working configuration andare not intended to limit the claimed invention in any way. A lightingcontrol interface circuit configured with such circuitry provides anumber of features, including but not limited to: galvanic isolationfrom lighting controller; recognition of 0-10V signal reverseconnection, such that when signal is reversed, minimum light outputpower may be applied; a 0-10V analog signal wherein 0V corresponds tominimum light and 10V corresponds to maximum light; current draw fromcontrol is 2.0 mA (which may be desirable, for example, for 0-10Vcontrol signals); and common mode noise voltage control by using theZener diodes Z1 and Z2 and the op-amp U2 input protection (the diodes D1and D2 and high input impedance of the op-amp U2).

Going back again to FIGS. 1A and 1B, the lighting control interfacecircuit 100/100 a includes an on-board signal generator 118 and a buffer112. As explained above, the signal generator 118 and the buffer 112 maybe, and in some embodiments are, used to provide an alternative or dummycontrol signal to the two terminals A and B of the interface connector110. Such a dummy control signal is provided so that when no actualcontrol signal is present at either of the two terminals A and B, theMCU 126 will detect the unsuppressed signal of the on-board signalgenerator 118 and therefore be informed that no actual control signal ispresent at either or both of the two terminals A and B. FIG. 4illustrates a possible configuration of the signal generator 118 and thebuffer 112. As may be seen, the signal generator 118 is implemented withan oscillator configuration that includes an op-amp U6 with an invertinginput, a non-inverting input, two power terminals, and an output, alongwith resistors R8, R9, R10, and R11, and a capacitor C11. The resistorR8 is connected to the output of the op-amp U6 and to a non-invertinginput of an op-amp U4 of the buffer 112. The resistor R9 is connectedbetween the output of the op-amp U6 and the inverting input of theop-amp U6. The resistor R10 is connected between the output of theop-amp U6 and the non-inverting input of the op-amp U6. The resistor R11is connected between the non-inverting input of the op-amp U6 and theisolated ground GND_(Iso) of the isolated power supply 122. Thecapacitor C11 is connected between the inverting input of the op-amp U6and the isolated ground GND_(Iso) of the isolated power supply 122. Thesecond internal supply +V_(Iso), −V_(Iso) of the isolated power supply122 is connected to the power terminals of the op-amp U6. The buffer 112is implemented with a differential amplifier configuration that includesop-amps U4 and U5, each including an output, an inverting input, anon-inverting input, and two power terminals, along with resistors R6and R7, a capacitor C10, and two pairs of serially connected diodes, D3and D4, and D5 and D6. Each pair of serially connected diodes, D3 andD4, and D5 and D6, are configured such that an anode of each diode inthe pair is connected to an anode of the other diode in the pair. Theresistor R6 is connected between the output of the op-amp U4 andterminal A of the two terminals A and B. The anode to anode connectionof the pair of serially connected diodes D3 and D4 is also connected tothe output of the op-amp U4. The second internal supply +V_(Iso),−V_(Iso) of the isolated power supply 122 is connected to the powerterminals of the op-amp U4, and the capacitor C10 is connected acrossthe power terminals. The inverting input of the op-amp U4 is connectedto the isolated ground GND_(Iso) of the isolated power supply 122. Thenon-inverting input of the op-amp U4 is connected to the resistor R8 ofthe signal generator 118 and to the inverting input of the op-amp U5.The resistor R7 is connected between the output of the op-amp U5 andterminal B of the two terminals A and B. The anode to anode connectionof the pair of serially connected diodes D5 and D6 is also connected tothe output of the op-amp U5. The second internal supply +V_(Iso),−V_(Iso) of the isolated power supply 122 is connected to the powerterminals of the op-amp U5. The second internal supply +V_(Iso),−V_(Iso) of the isolated power supply 122 is also connected to thecathode of each diode in the two pairs of serially connected diodes, D3and D4, and D5 and D6.

In operation, the signal generator 118 generates a low frequency squarewave (depending on the values of the resistors R8, R9, R10, and R11 andthe capacitor C11), and the op-amps U4 and U5 of the buffer 112 bufferthe square wave, but the outputs of the op-amps U4 and U5 have oppositepolarity. Through the relatively high values of the resistors R6 and R7,the outputs of the op-amps U4 and U5 are applied to the two terminals Aand B. If the two terminals A and B are connected to a control signal(for example but not limited to a 0-10V signal or a DALI signal), thatcontrol signal will override the square wave generated by the signalgenerator 118 with high output impedance (for example, the op-amps U4,U5, and U6, and the resistors R6 and R7). The output of theopto-isolation amplifier U3 in the isolation amplifier 120 presents thesignal amplitude and polarity information of that control signal. On theother hand, if the input at the two terminals A and B is open (i.e.,there is no control signal or signals received at one or both of the twoterminal A and B), the output of the opto-isolation amplifier U3 in theisolation amplifier 120 presents the square wave.

In some embodiments, the op-amps U4, U5, and U6 are all TS912 op-amps bySTMicroelectronics, the resistors R6 and R7 each have a value of 430KΩ,the resistors R8 and R11 each have a value of 10KΩ, the resistors R9 andR10 each have a value of 100KΩ, the capacitors C10 and C11 each have avalue of 100 nF, and the diode pairs D3 and D4, and D5 and D6, are eachimplemented with a BAV99 silicon diode pair. Again, numerous othersuitable component manufacturers and component types and componentvalues may be, and in some embodiments are, used, and any specificexamples provided herein merely illustrate one possible workingconfiguration and are not intended to limit the claimed invention in anyway. A lighting control interface circuit 100/100 a configured with suchsignal generation capability provides a number of features, includingrecognition of input open condition, such that when no control signal(e.g., 0-10V, etc) is applied, a default light output signal (e.g., fulllight output power, or other desired default light output power) maythen be provisioned by the microcontroller unit or other processor. Aswill be further appreciated in light of this disclosure, using aself-contained alternative signal source with high output impedance toapply a dummy or otherwise sacrificial test signal to the inputterminals of the interface circuit to identify the conditions of noinput signal connection may be carried out using signal types other thansquare waves (e.g., sine wave, saw tooth wave, or any other wave shape),and the claimed invention is not intended to be limited to anyparticular signal type or particular set of parameters. In short, anydummy signal may be, and in some embodiments is, used, so long as theprocessor of the interface circuit is able to detect the presence of thedummy signal when no control signal is applied.

Again referring back to FIGS. 1A and 1B, the lighting control interfacecircuit 100/100 a also includes the signal translator 124. In operation,when a lighting control signal or signals is applied to the twoterminals A and B of the interface connector 110, the output of theisolation amplifier 120 presents the signal. For a 0-10V signal, theoutput of the isolation amplifier 120 presents the signal amplitude andpolarity information. For a DALI control signal, the output of theisolation amplifier 120 presents the high or low and input polarityinformation of the DALI signal. The signal translator 124 may be, and insome embodiments is, configured to translate the output of the isolationamplifier 120 into a logic DALI signal, such as but not limited to a TTLor CMOS logic signal, or any other suitable lighting control signal.FIG. 5 shows one possible configuration of the signal translator 124. Asmay be seen, the signal translator 124 in FIG. 5 is implemented with awindow comparator circuit formed of op-amps U7 and U8, each having aninverting input, a non-inverting input, an output, and two powerterminals, along with resistors R12, R13, R15, R16, R17, R18, R19, andR20. The power terminals of each op-amp U7 and U8 are connected to thepositive portion of the third internal supply +V_(DD2) of the isolatedpower supply 122 and to ground. The resistors R12, R13, and R15 areconnected in series between the positive portion of the third internalsupply +V_(DD2) of the isolated power supply 122 and ground. Aconnection point between the resistors R12 and R13 is connected to theinverting input of the op-amp U7. A connection point between theresistors R13 and R15 is connected to the inverting input of the op-ampU8. The resistors R16 and R17 are each connected to an input of thesignal translator 124, which receives the output signal Vout from theisolation amplifier 120. The resistor R16 is also connected to thenon-inverting input of the op-amp U7, and the resistor R17 is alsoconnected to the non-inverting input of the op-amp U8. The resistor R18is connected between the non-inverting input of the op-amp U7 and theoutput of the op-amp U7. The resistor R19 is connected between thenon-inverting input of the op-amp U8 and the output of the op-amp U8.The outputs of the op-amps U7 and U8 and interconnected. The resistorR20 is connected between the interconnected outputs of the op-amps U7and U8 and the positive portion of the third internal supply +V_(DD2) ofthe isolated power supply 122. In operation, the signal translator 124receives the output of the isolation amplifier 120 and translates itinto, for example, a logic DALI signal, at its output (i.e., theinterconnected outputs of the op-amps U7 and U8). Note that an outputside of the isolated amplifier 120 has the same power supply as theop-amps U7 and U8, which in FIG. 5 is the positive portion of the thirdinternal supply +V_(DD2) of the isolated power supply 122.

In some embodiments, the op-amps U7 and U8 are implemented with anLM2903 dual differential comparator by STMicroelectronics, the resistorsR12, R13, R15, R16, R17, and R20 each have a value of 10KΩ, and theresistor R18 and R19 each have a value 1MΩ. Again, numerous othersuitable component manufacturers and component types and componentvalues may be, and in some embodiments are, used, and any specificexamples provided here merely illustrate one possible configuration andare not intended to limit the claimed invention in any way. A lightingcontrol interface circuit configured with such signal translationcapability, along with the functionality described in reference to FIG.4, provides a number of features and capabilities. For instance,components intended to process one particular control signal are able towithstand the presence of a different type of control signal applied toone of the two input terminals A and B of the interface circuit 100/100a, including the full range of such a particular control signal. Thus,such an interface circuit is capable of receiving, for example, either aDALI or a 0-10V control signal on the same input terminal(s), and isfurther capable of at least one or more of open input recognition, inputlinearity, and reverse and off-range recognition.

Referring yet again back to FIGS. 1A and 1B, the lighting controlinterface circuit 100/100 a includes the transmitter 126. Thetransmitter 126 allows for lighting control standards that usebidirectional communication from and to a lighting controller to be usedby the interface circuit 100/100 a. FIG. 6 shows a transmitter 116 inone possible configuration for this purpose. The transmitter 116 of FIG.6 is implemented with a photo-MOS relay circuit U9 and a resistor 21.The photo-MOS relay circuit U9 includes four terminals, two of which areconnected to the two input terminals A and B, one of which is connectedto the resistor R21, and the remaining of which is connected to the MCU126. The resistor R21 is also connected to the positive portion of thethird internal supply +V_(DD2) of the isolated power supply 122, fromwhich the transmitter 116 receives power. Thus, the transmitter 116 hasthe same power supply as the signal translator 124. The transmitter 116,in operation, couples responses and other information from the MCU 126back to the lighting controller 104/104 a via the interface connector110. Note that the MCU 126 may, and in some embodiments does, setcommunication timing, so that a response or responses sent back to thelighting controller 104/104 a do not interfere with the receipt of oneor more control signals being received on the two input terminals A andB. In some embodiments, the transmitter 116 is switched in and out ofcircuit by the MCU 126, if so desired. Numerous other bidirectionalcommunication schemes may be, and in some embodiments are, used, and theclaimed invention is not intended to be limited to any particular one.Of course, some embodiments do not include bidirectional communicationcapability.

Still again referring back to FIGS. 1A and 1B, the lighting controlinterface circuit 100/100 a includes an MCU 126, which may be, and insome embodiments is, any suitable processor and/or microprocessorcapable of carrying out the various functionalities describedthroughout. In general, MCU 126 is able to receive one or more inputs(such as but not limited to an output signal associated with a firstlighting protocol, protocol #1, and an output signal associated with asecond lighting protocol, protocol #2), and to generate one or moreoutput drive signals, which are provided to a ballast/ driver circuit150 that is connected to the interface circuit 100 or is a part of theinterface circuit 100 a. The one or more output drive signals may be,and in some embodiments are, for example but not limited to, a pulsewidth modulated (PWM) dimming signal or other desired lighting controlsignal. In some embodiments, the MCU 126 is configured to respond torequests of the lighting controller 104/104 a and/or other modulerequests by way of the transmitter 116, as previously discussed. The MCU126 includes a number of input/output ports capable of receiving andoutputting signals as described throughout, as well as a number ofembedded routines for interrogating received lighting control signalsand generating appropriate output drive signals. The MCU 126 may, and insome embodiments does, include other functionality, such as but notlimited to analog-to-digital converters (ADCs) for processing analoginputs, voltage measuring capability (e.g., V_(DC), V_(average),V_(peak) and/or V_(peak-to-peak)), and memory for storing signal dataand/or other data, and/or embedded routines and/or other instructions tobe executed by the MCU 126. In some embodiments, the MCU 126 isimplemented in hardware, such as with gate-level logic or purpose-builtsilicon. In some embodiments, the MCU 126 is implemented with anycombination of hardware, software, and/or firmware so as to provide thevarious functionalities as described.

A flowchart of a method of processing lighting control signals isillustrated in FIG. 7. The elements of the flowchart are herein denoted“processing blocks” and represent computer software instructions orgroups of instructions. Alternatively, the processing blocks representsteps performed by functionally equivalent circuits such as a digitalsignal processor circuit or an application specific integrated circuit(ASIC). The flowchart does not depict the syntax of any particularprogramming language. Rather, the flowchart illustrates the functionalinformation one of ordinary skill in the art requires to fabricatecircuits or to generate computer software/firmware to perform theprocessing required in accordance with embodiments. It should be notedthat many routine program elements, such as initialization of loops andvariables and the use of temporary variables, are not shown. It will beappreciated by those of ordinary skill in the art that unless otherwiseindicated herein, the particular sequence of steps described isillustrative only and may be varied without departing from the spirit ofthe invention. Thus, unless otherwise stated, the steps described beloware unordered, meaning that, when possible, the steps may be performedin any convenient or desirable order. More specifically, FIG. 7illustrates a method that may be carried out by the MCU 126 or otherprocessor of the lighting control interface circuit 100/100 a, inaccordance with embodiments.

The MCU receives a first potential lighting control signal, step 701,and receives a second potential lighting control signal, step 703.Referring once more back to FIGS. 1A and 1B, for example, the firstpotential lighting control signal and the second potential lightingcontrol signal may be, and in some embodiments are, the result of alighting control signal being applied to the two terminals A and B, suchas but not limited to a 0-10V or a DALI compliant signal or any othersignal that is compliant with a given lighting protocol. Alternatively,the first and second potential lighting control signals received may bethe result of no lighting control signal being applied to the twoterminals A and B (i.e., an open input condition). In some embodiments,the first and second potential lighting control signals are receivedsimultaneously with at least some overlap in the receiving time period,and in some embodiments, sequentially with no overlap.

The method continues with determining if the first signal indicates anopen input, step 705. To recognize the open input condition, a signalgenerator and a buffer, such as but not limited to the signal generator118 and the buffer 112, may be and in some embodiments are used, aspreviously explained. In some embodiments, the signal generator isconfigured to generate a 270 HZ square wave ±5V, although any suitabledummy control signal may be and in some embodiments is used, and thedummy control signal shape, frequency, and/or amplitude may vary. Thebuffer 112 may be, and in some embodiments is, used to drive the twoterminals A and B through relatively high value resistors. In general,any impedance value may be used that is substantially higher than theoutput impedance of the lighting controller 104/104 a connected to theinterface circuit 100/100 a, or that otherwise allows suppression of thedummy control signal when an actual control signal is present at one ormore of the two terminals A and B. With reference to FIGS. 3 and 4, theoutputs of the op-amps U4 and U5 of the buffer 112 are in oppositephase. If the input terminal open condition is true, the lightingcontrol interface circuit 100/100 a will output, as a first lightingprotocol protocol #1, received by the MCU 126, the square wave with anaverage voltage of about zero, and the peak-to-peak value at the outputis a non-zero (substantially −1V here, but other embodiments willprovide different values). The MCU 126 may, and in some embodimentsdoes, measure this output and make the determination of step 705 basedon measured or otherwise computed results. If the first signal indicatesan open input, then the method continues with setting output lightingpower to a default value, step 707. The default value may be, and insome embodiments is, a max power, a min power, or any other acceptablepredetermined power level.

If the first signal does not indicate an open input condition, then itis determined if the first signal indicates a first protocol, step 709.Referring to the use of a 270 Hz square wave signal generator again, ifthe two terminals A and B are connected to a 0-10V control signal, thenthe 270 Hz square wave will be suppressed and disappeared at the outputof the isolation amplifier 120 (i.e., the first lighting protocolprotocol #1 received by the MCU 126), because that 0-10V control signalhas relatively low impedance (e.g., output impedance of a 0-10Vcompliant lighting controller is ≤100Ω) compared to the 430KΩ outputimpedance associated with the 270 Hz square wave generator.

In more detail, and with respect to the determinations at steps 705 and709 in the context of FIGS. 3 and 4, the output dynamic range of theisolation amplifier 120 is largely based on the polarities of theapplied lighting control signal. If the lighting control signal isconnected in its non-inverted state, the output range of the isolationamplifier 120 is above V_(DD2)/2, which may be 2.5V in some embodiments(assuming V_(DD2)=5.0VDC). If the lighting control signal is connectedin reversed polarity, the output signal range at the output of theisolation amplifier 120 is below 2.5V. Both these conditions maytherefore be detected by the MCU 126. If a lighting control signal isnot connected to the two terminals A and B, the output signal of theisolation amplifier 120 is, for example, a dummy control signal, such asbut not limited to the 270 HZ square wave signal described above thatalternates up and down across 2.5V. In such embodiments, thismanifestation of the dummy control signal, which is output by theisolation amplifier 120, is then low-pass filtered (via the resistor R5and the capacitor C9) and fed to an ADC of the MCU 126, so that thesignal condition is then recognized or otherwise identified by the MCU126. Thus, the MCU 126 is configured to recognize the polarity andamplitude of the input voltage of signal applied at the two terminals Aand B, such as whether the voltage is within ±10V or other suchprotocol-based bipolar voltage range. The MCU 126, in some embodiments,is configured to test for an open input condition by determining thatthe output of the isolation amplifier 120 has an average output voltageof substantially zero (within an acceptable tolerance, such as +/−250mV), and an absolute voltage that is a significant non-zero (also withinan acceptable tolerance, such as +/−5%). As will be appreciated, otheroutput parameters that reflect a unique manifestation that may bedetected by the MCU 126 may be, and in some embodiments are, used aswell, or alternatively.

If the first signal indicates a first protocol, then the methodcontinues with setting output lighting power according to the firstprotocol (e.g., 0-10V protocol, or other desired standard), step 711. Inother words, the output drive signal provided is set according to thefirst lighting protocol. On the other hand, if the first signal does notindicate the first protocol, then the method continues with determiningif the second signal indicates a second protocol, step 713. This iscarried out in a similar fashion as described with reference to thedetermination of the first protocol, except that the measured orcomputed parameters would be those uniquely indicative of the secondprotocol. For example, the requirement of a DALI-compliant interfaceinput voltage is in the range of ±22.5V, with rising and falling edgesof less than 100 μs. These requirements may also be configured into orotherwise met by first protocol (e.g., 0-10V) interface portion of theinterface circuit, which also meets the galvanic isolation requirementof DALI. As previously explained, a DALI control signal may effectivelybe extracted or otherwise recovered from the 0-10V portion of thecontrol signal interface circuit using the signal translator 124. Thus,the DALI portion of the interface circuit receives its input from theoutput of the isolation amplifier 120. If a DALI control signal isindeed being applied at the two terminals A and B, then this output willbe a DALI signal in reverse polarity. The signal translator 124 adjuststhe levels of the output signal to provide a DALI signal havingappropriate logic levels. The positive feedback of the op-amps U7 and U8introduces hysteresis to improve edges of the DALI signal intoappropriate logic levels. The MCU 126 may be, and in some embodimentsis, configured, for instance, to correct the polarity and recognize theDALI message. Thus, if the second signal indicates a second protocol,then the method continues with setting output lighting power accordingto the second protocol (e.g., DALI protocol, or other desired standard),step 715. On the other hand, if the second signal does not indicate asecond protocol, then the process may continue with, for example,indicating an error or default condition (e.g., no light, error message,etc), step 717.

The MCU 126 or other suitable processing environment is capable ofassessing if a lighting control signal is actually being applied to oneor both of the two terminals A and B of the interface connector 110, andif so, determining with which standard it complies with. The MCU 126assesses the output signals from the interface circuit and makes adetermination as to which one is most likely a manifestation of asupported lighting control protocol signal, or an open input. The orderand manner in which the various output signals are assessed need not belimited to the examples provided herein.

Numerous variations will be apparent in light of this disclosure. Forinstance, in some embodiments, note that the interface may only be forreceiving one type of lighting control protocol (rather than multipletypes). In such cases, the MCU may be used, for example, to determinewhen an actual lighting control signal compliant with that protocol isapplied or when there is no lighting control signal applied. Likewise,other embodiments may include additional or less functionality. Forinstance, while this embodiment allows for bi-directional communicationbetween the lighting controller and the lighting control interfacecircuit (using the transmitter), other embodiments need not include suchfunctionality. Moreover, note that other embodiments may integrate oneor more functional modules shown into other modules, as demonstrated inFIG. 1B. In other embodiments, the lighting control interface circuitmay be integrated directly into the light controller module.Alternatively, some of the lighting control interface circuit may beintegrated into the lighting controller, and other portions of thelighting control interface circuit may be integrated into theballast/light driver module. The degree of integration may vary from oneembodiment to the next.

The methods and systems described herein are not limited to a particularhardware or software configuration, and may find applicability in manycomputing or processing environments. The methods and systems may beimplemented in hardware or software, or a combination of hardware andsoftware. The methods and systems may be implemented in one or morecomputer programs, where a computer program may be understood to includeone or more processor executable instructions. The computer program(s)may execute on one or more programmable processors, and may be stored onone or more storage medium readable by the processor (including volatileand non-volatile memory and/or storage elements), one or more inputdevices, and/or one or more output devices. The processor thus mayaccess one or more input devices to obtain input data, and may accessone or more output devices to communicate output data. The input and/oroutput devices may include one or more of the following: Random AccessMemory (RAM), Redundant Array of Independent Disks (RAID), floppy drive,CD, DVD, magnetic disk, internal hard drive, external hard drive, memorystick, or other storage device capable of being accessed by a processoras provided herein, where such aforementioned examples are notexhaustive, and are for illustration and not limitation.

The computer program(s) may be implemented using one or more high levelprocedural or object-oriented programming languages to communicate witha computer system; however, the program(s) may be implemented inassembly or machine language, if desired. The language may be compiledor interpreted.

As provided herein, the processor(s) may thus be embedded in one or moredevices that may be operated independently or together in a networkedenvironment, where the network may include, for example, a Local AreaNetwork (LAN), wide area network (WAN), and/or may include an intranetand/or the internet and/or another network. The network(s) may be wiredor wireless or a combination thereof and may use one or morecommunications protocols to facilitate communications between thedifferent processors. The processors may be configured for distributedprocessing and may utilize, in some embodiments, a client-server modelas needed. Accordingly, the methods and systems may utilize multipleprocessors and/or processor devices, and the processor instructions maybe divided amongst such single- or multiple-processor/devices.

The device(s) or computer systems that integrate with the processor(s)may include, for example, a personal computer(s), workstation(s) (e.g.,Sun, HP), personal digital assistant(s) (PDA(s)), handheld device(s)such as cellular telephone(s) or smart cellphone(s), laptop(s), handheldcomputer(s), or another device(s) capable of being integrated with aprocessor(s) that may operate as provided herein. Accordingly, thedevices provided herein are not exhaustive and are provided forillustration and not limitation.

References to “a microprocessor” and “a processor”, or “themicroprocessor” and “the processor,” may be understood to include one ormore microprocessors that may communicate in a stand-alone and/or adistributed environment(s), and may thus be configured to communicatevia wired or wireless communications with other processors, where suchone or more processor may be configured to operate on one or moreprocessor-controlled devices that may be similar or different devices.Use of such “microprocessor” or “processor” terminology may thus also beunderstood to include a central processing unit, an arithmetic logicunit, an application-specific integrated circuit (IC), and/or a taskengine, with such examples provided for illustration and not limitation.

Furthermore, references to memory, unless otherwise specified, mayinclude one or more processor-readable and accessible memory elementsand/or components that may be internal to the processor-controlleddevice, external to the processor-controlled device, and/or may beaccessed via a wired or wireless network using a variety ofcommunications protocols, and unless otherwise specified, may bearranged to include a combination of external and internal memorydevices, where such memory may be contiguous and/or partitioned based onthe application. Accordingly, references to a database may be understoodto include one or more memory associations, where such references mayinclude commercially available database products (e.g., SQL, Informix,Oracle) and also proprietary databases, and may also include otherstructures for associating memory such as links, queues, graphs, trees,with such structures provided for illustration and not limitation.

References to a network, unless provided otherwise, may include one ormore intranets and/or the internet. References herein to microprocessorinstructions or microprocessor-executable instructions, in accordancewith the above, may be understood to include programmable hardware.

Unless otherwise stated, use of the word “substantially” may beconstrued to include a precise relationship, condition, arrangement,orientation, and/or other characteristic, and deviations thereof asunderstood by one of ordinary skill in the art, to the extent that suchdeviations do not materially affect the disclosed methods and systems.

Throughout the entirety of the present disclosure, use of the articles“a” and/or “an” and/or “the” to modify a noun may be understood to beused for convenience and to include one, or more than one, of themodified noun, unless otherwise specifically stated. The terms“comprising”, “including” and “having” are intended to be inclusive andmean that there may be additional elements other than the listedelements.

Elements, components, modules, and/or parts thereof that are describedand/or otherwise portrayed through the figures to communicate with, beassociated with, and/or be based on, something else, may be understoodto so communicate, be associated with, and or be based on in a directand/or indirect manner, unless otherwise stipulated herein.

Although the methods and systems have been described relative to aspecific embodiment thereof, they are not so limited. Obviously manymodifications and variations may become apparent in light of the aboveteachings. Many additional changes in the details, materials, andarrangement of parts, herein described and illustrated, may be made bythose skilled in the art.

What is claimed is:
 1. A lighting control interface circuit, comprising:an interface connector configured to receive a lighting control signal;a control signal processing circuit operatively coupled to the interfaceconnector and having a first processing section that provides a firstoutput signal at a first output; and a processor configured to receivethe first output signal via the first output, to determine if a lightingcontrol signal is being applied at the interface connector based on thefirst output signal, and to determine if the lighting control signalapplied at the interface connector complies with one of a first lightingcontrol protocol and a second lighting control protocol.
 2. The lightingcontrol interface circuit of claim 1, further comprising: a signalgenerator circuit operatively coupled to the interface connector andconfigured to provide a dummy control signal at an output of the controlsignal processing circuit as an indicator to the processor that nolighting control signal is currently applied to the interface connector.3. The lighting control interface circuit of claim 2, wherein theprocessor is further configured to detect the dummy control signal at anoutput of the control signal processing circuit.
 4. The lighting controlinterface circuit of claim 2, wherein a lighting control signal appliedto the interface connector overrides the dummy control signal.
 5. Thelighting control interface circuit of claim 2, wherein the processor isconfigured to detect the dummy control signal at the first output whenno lighting control signal is applied to the interface connector.
 6. Thelighting control interface circuit of claim 1, wherein the controlsignal processing circuit further comprises a second processing sectionoperatively coupled to the first output and configured to provide asecond output signal at a second output.
 7. The lighting controlinterface circuit of claim 6, wherein the processor is furtherconfigured to receive the second output signal and to determine if thesecond output signal complies with a lighting control protocol in aplurality of lighting control protocols.
 8. The lighting controlinterface circuit of claim 1, wherein the first processing sectioncomprises an isolation amplifier, and wherein the lighting controlinterface circuit further comprises an isolated power supply configuredto provide power to one side of the isolation amplifier.
 9. The lightingcontrol interface circuit of claim 1, further comprising: a transmittercommunicatively coupled between the processor and the interfaceconnector, and configured to allow the processor to communicate with alighting controller connected to the interface connector.
 10. A lightingcontrol interface circuit, comprising: an interface connector configuredto receive a lighting control signal that is compliant with a lightingcontrol protocol in a plurality of lighting control protocols; a controlsignal processing circuit operatively coupled to the interfaceconnector, wherein the control signal processing circuit comprises anisolation amplifier configured to provide a first output signal at afirst output, and a signal translator operatively coupled to the firstoutput and configured to provide a second output signal at a secondoutput; and a processor configured to receive the first and secondoutput signals and to determine if a lighting control signal applied atthe interface connector complies with a lighting control protocol in theplurality of lighting control protocols.
 11. The lighting controlinterface circuit of claim 10, further comprising at least one of: anisolated power supply configured to provide power to one side of theisolation amplifier; and a transmitter communicatively coupled betweenthe processor and the interface connector configured to allow theprocessor to communicate with a lighting controller connected to theinterface connector.
 12. The lighting control interface circuit of claim11, further comprising: a signal generator circuit operatively coupledto the interface connector and configured to provide a dummy controlsignal at an output of the control signal processing circuit as anindicator to the processor that no lighting control signal is currentlyapplied to the interface connector.
 13. The lighting control interfacecircuit of claim 12, wherein the processor is further configured todetect the dummy control signal at an output of the control signalprocessing circuit.
 14. The lighting control interface circuit of claim12, wherein the processor is configured to detect the dummy controlsignal at the first output when no lighting control signal is applied tothe interface connector.